In the field of microelectronics, an electrostatic discharge may occur at any time throughout the service life of an integrated circuit, and constitute a real problem for the reliability of the electronic components or modules of this integrated circuit, as well as a major cause of failure.
An electrostatic discharge generally results in a current peak varying in size (amplitude, magnitude) and brevity (time) between two terminals of an electronic module of the integrated circuit.
For an electrostatic discharge to take place, it is necessary that a first terminal of the module receives the discharge, e.g. on contact with an electrically charged body, and that a second terminal acts as a ground, e.g. by being in contact with a metal object.
Usually, an electrostatic discharge takes place when the integrated circuit is powered off, between two terminals from among the power supply terminal, the reference terminal, or one of the signal terminals, coupled to said module.
An ESD protection device is aimed at absorbing this current peak as much as possible in order to prevent it from flowing into the module, or a possible surge at the module's terminals.
There are various protections against electrostatic discharge, notably MOS hybrid operation transistors.
Hybrid operation transistors are MOS transistors comprising a parasitic bipolar transistor the operation of which involves an operation of this bipolar transistor and an operation of the MOS transistor in a sub-threshold mode.
The principle of a hybrid operation of a MOS transistor has been highlighted in the article by Galy, et al. “Ideal Gummel curves simulation of high current gain vertical BIMOS NPN transistor”, INT. J. ELECTRONICS, 1996, vol. 80 No. 6, 717-726 (incorporated by reference). This article is a theoretical study carried out on a vertical structure transistor having a gate length (channel length) of the order of a micron and validated by simulations, without any application of such a hybrid operation being mentioned.
Such a MOS hybrid operation transistor notably has the advantage of being resistant to ionizing radiation and it may generally be employed for mass consumer, space or military applications, in the digital and analogue fields.
The use of such a component in the context of the protection of circuits against electrostatic discharge has notably been described in International Patent Application No. WO 2011 089179 (and its U.S. equivalent patent publication 2013/0141824).
However, some ESD protection devices described in this international application may, in some cases, present some drawbacks. It has notably been observed that when the device is coupled between a signal terminal (input/output terminal) and a power supply terminal of the integrated circuit, and the environment of the integrated circuit is not correctly controlled, it is liable to be triggered during the operation of the integrated circuit (therefore in the absence of any electrostatic discharge), e.g. when the potential difference between the power supply terminal and the signal terminal is greater than or equal to the trigger threshold of the protection device.
This is liable to damage at least one part of the integrated circuit and/or generate operating errors.
There is, moreover, a need to reduce as much as possible the surface occupied by the protection device, in particular when it is distributed over the different signal terminals coupled to different electronic components or modules of the integrated circuit.